1. Field of the Invention
This invention relates generally to data processing systems having data processing operations provided over a common input/output bus, and more particularly with a universal peripheral controller for controlling various types of peripherals coupled to the bus.
2. Description of the Prior Art
Many data processing systems include a common bus to which a plurality of units are connected for the transfer of information. The bus permits any two units to communicate with each other at a given time via a common (shared) signal path. Any unit wishing to communicate, requests the bus cycle. When that bus cycle is granted, that unit becomes the master and may address any other unit in the system as the slave. Most transfers are in the direction of a master to a slave. Some types of bus interchange require a response cycle (read memory, for example). In cases where a response cycle is required, the requester assumes the role of the master, indicates a response is required, and identifies itself to the slave. When the required information becomes available (depending on slave response time), the slave now assumes the role of the master and initiates a transfer to the requesting unit. This completes the interchange which has taken two bus cycles. Intervening time on the bus between these two cycles may be used for other system traffic not involving these two units.
A master may address any other unit on the bus as a slave. It does this by placing the slave address on the address leads. There may be 24 address leads, for example, which can have either of two interpretations depending on the state of an accompanying control lead, called the memory reference cycle. In essence when the memory is being addressed, the bus enables up to 2.sup.24 bytes to be directly addressed to memory. When units are passing control information, data or interrupts, they address each other by a channel number. The channel number allows up to 2.sup.10 channels to be addressed by the bus. Along with the channel number a 6 bit function code is passed which specifies which up to 2.sup.6 possible functions this transfer implies.
A typical prior art data processing system utilizing a bus is shown on FIG. 1. A multiline bus 100 coupled with memory 1 102 to memory N 104, such memories having the highest priority and with the central processor 106 having the lowest priority. Also connected on the bus may be included, for example, a scientific-arithmetic unit 108 and various controllers 110, 112, 114 Controller 110 may be coupled to control, for example, 4 unit record peripheral devices 216. Controller 112 may be used to provide communication control via modem devices; whereas controller 114 may be utilized to control mass storage devices, such as a tape peripheral device 118 and a disk peripheral device 120. Any one of the devices coupled with the bus 100 may address a memory or any other unit connected to the bus. Thus tape peripheral 118 may, via controller 114, address memory 102. Each of such units directly connected to bus 100 includes a tie-breaking logic in the event that two units request simultaneous service to the bus further.
A channel number exists for every end point in the particular system with the exception of the memory type processing elements which are identified by the memory address. A channel number is assigned for each such device. Full duplex devices, as well as half duplex devices, utilize two channel numbers. Output only or input only devices use only one channel number each. Channel numbers are easily variable and accordingly one or more hexidecimal rotary switches (thumb wheel switches) may be utilized for each such unit or devices connected to the bus to indicate a devices address. Thus when a system is configured, the channel number may be designated for each particular unit or device connected to the bus, as may be appropriate for that particular system. Units with multiple inputs/outputs generally will require a block of consecutive channel numbers By way of example, a 4 port unit may use rotary switches to assign the upper 7 bits of a channel number and may use the lower order 3 bits thereof to define the port number to distinguish input ports from output ports. The channel number of the slave unit will appear on the address bus for all non-memory transfers. Each unit compares that number with its own internally stored number (internally stored by means of the rotary switches). The unit which achieves a comparison match is, by definition, the slave, and must respond to that cycle. Generally, no two points in a single system will be assigned to the same channel number. The function codes may designate output or input operations. All odd function codes designate output transfers (write), while all even function codes designate input transfer requests (read). The central processor examines the least significant bit of a 6 bit function code field for an input/output command and uses a bus lead to designate the direction.
A unique device identification number is assigned to every different type of device or unit which is connected to the bus. This number is presented on the bus in response to the input function command, entitled input device identification.
A unit wishing to interrupt the central processor requests the bus cycle. When this bus cycle is granted, the unit places its interrupt vector on the bus, the interrupt vector includes the channel number of the central processor and the interrupt level number. The unit thus provides, as its interrupt vector, the master's channel number and its interrupt level number. If this is the central processor's channel number, the central processor will accept the interrupt if the level presented is numerically smaller than the current internal central processor level and if the central processor has not just accepted another interrupt.
In this type of system different units have different priorities in order to obtain bus cycles. For example, the memory has the highest priority and the central processor has the lowest priority, and they reside physically at opposite ends of the bus 100. Other units occupy intermediate positions and have priority which increases relative to their proximity to the memory end of the bus.
More detail is disclosed in regard to the above type of bus system in the following U.S. patents. The subject patents pertain to the proprietary bus system of Honeywell known in the trade as Megabus*. FNT *Megabus--a trademark of Honeywell Information Systems Inc.
(a) Data Processing System Providing Split-Bus Cycle Operation by Frank V. Cassarino, Jr. et al, issued Dec. 14, 1976, and having U.S. Pat. No. 3,997,896. PA1 (b) Data Processing System Providing Locked Operation of Shared Resources by George J. Barlow et al, issued Dec. 28, 1976 and having U.S. Pat. No. 4,000,485. PA1 (c) Data Processing System Having Distributed Priority Network by George J. Barlow, issued June 14, 1977, and having U.S. Pat. No. 4,030,075. PA1 (d) Data Processing System Having Distributed Priority Network with Logic for Deactivating Information Transfer Requests by George J. Barlow, issued June 20, 1978, and having U.S. Pat. No. 4,096,569. PA1 (e) Apparatus for Processing Data Transfer Requests in a Data Processing System by Frank V. Cassarino, Jr. et al, issued Nov. 23, 1976, and having U.S. Pat. No. 3,993,981. PA1 (f) Data Processing System Having a Data Integrity Technique by George J. Barlow, issued Nov. 30, 1976, and having U.S. Pat. No. 3,995,258.
It can be seen that with this hierarchical bus process system and the diversity of peripheral systems attached to the bus by different types of controllers that it was necessary to have a universal peripheral controller which could control different types of devices, and eliminate the necessity of having different controllers for different peripherals.
Accordingly a new architecture was necessary, so that the controller would provide equal access to all peripherals coupled to the bus and not lock out or deny access to any peripheral because of priority problems. In order that the controller be cheaper yet more efficient it was required that data transfers on the bus be performed autonomously under local control by commercially available direct memory access (DMA) chips once tee Megabus microprocessor (.mu.P) had set up the transfer requirements. In this way the .mu.P would be left free to attend to other tasks while the DMA chips could oversee the transfer of information between devices coupled to the .mu.P. Thus several levels of simultaneity could be achieved for data processors.
One problem that presented itself in achieving this result was the fact that the architecture, in order to provide equal access to the bus by various peripherals required a rotating priority scheme, wherein each port, to which a peripheral device was attached, was to receive up to 4 bytes of information at one given time then proceed to the other ports in round robin fashion. However the commercially available DMA chip has a priority scheme which awards the bus channel to the highest priority channel when both channels presented requests for the bus simultaneously.